1. Field
This disclosure relates generally to memories, and more specifically, to a memory having a negative voltage write assist circuit and method therefor.
2. Related Art
Static random access memories (SRAMs) are generally used in applications requiring high speed, such as memory in a data processing system. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. The SRAM cell is only stable in one of two possible voltage levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of a SRAM cell is an important issue. The SRAM cell must be stable against transients, process variations, soft error, and power supply fluctuations which may cause the cell to inadvertently change logic states. Also, the SRAM cell must provide good stability during read operations without harming speed or the ability to write to the cell.
However, good read stability can make it difficult to write to the memory cells. Also, process variations can cause some cells of the array to be more difficult to write than others. One way to have both good write performance and good read stability is to lower the memory array power supply voltage for write operations and raise the memory array power supply voltage for read operations. In addition, the write performance can be improved further by lowering the logic low bit line voltage below ground during the write operation. Typically, a capacitor bootstrapping circuit is used to boost the bit line voltage negative. However, a bootstrap circuit requires the use of a write driver circuit with relatively large transistors. Also, the ratio of capacitance between the bit line and the bootstrapping circuit is difficult to trim for different voltages.
Therefore, what is needed is a memory and a method for operating the memory that solves the above problems.